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How to enable the backside cache of my G4/400 Ugrade Card?

PostPosted: 11 Nov 2004, 12:04
by yellomike
Hello,

how to enable the backside cache of my G4/400 Ugrade Card under yellowdog 3.0.1 and how to check if the cache is enabled correctly?

enablling the level2 cache of my g4/400 card

PostPosted: 12 Nov 2004, 18:10
by yellowdog
Hello,

finally i get it!

you have to make the approcriate l2cr entry in the "more kernel arguments" field of
the BootX controlfield under MacOS9 like:

lcr=0xb9080000

(ATTENTION: it's the value of MY card, you have to make the appropriate l2cr entry of your card in this field: to find out the value for your card, take e.g the Powerlogix CPU Director 1.5f6 Programm (under Macos9) and take the appropriate value out of the l2 field!! ... then entry the value in the textfield "more kernel arguments" field of BootX)

To check if your l2-cache is enabled under linux open a shell from the Terminal and do
the following command:

cat /proc/sys/kernel/l2cr

the message must be something like this:

0xb9080000: L2 enabled, no parity, 1MB, +2 clock, pipelined burst SRAM, write-through, 0.5ns hold

if you have no sucess the message is something like this

:0x00000000: L2 disabled, no parity, 2MB, c
lock disabled, flow-through burst SRA M, copy-back, 0.5ns hold

... sorry for my english ;-)

Re: enablling the level2 cache of my g4/400 card

PostPosted: 25 Dec 2004, 23:39
by virgule
yellowdog wrote:you have to make the approcriate l2cr entry in the "more kernel arguments" field of the BootX controlfield under MacOS9 like:

lcr=0xb9080000

[...]

To check if your l2-cache is enabled under linux open a shell from the Terminal and do
the following command:

cat /proc/sys/kernel/l2cr

the message must be something like this:

0xb9080000: L2 enabled, no parity, 1MB, +2 clock, pipelined burst SRAM, write-through, 0.5ns hold


Thanks for such a great information! However, before I reboot i'd like to know something for sure: -How to know the value (0xXXXXXXXX) from linux side?

performing 'cat /proc/sys/kernel/l2cr' on my system output:

[andrew @ andrew]$ cat /proc/sys/kernel/l2cr
0x68dff740: disabled, parity, 512KB, +2 clock, flow-through burst SRAM, data only, ZZ enabled, write-through, testing, (reserved3)ns hold, DLL slow, diff clock, DLL bypass

Does it mean i have to pass 'lcr=0x68dff740 ' as a bootx arguments?