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Developing for Power, Cell

The Power Architecture
The Power ecosystem maintains a wonderful binary compatibility over more than a decade of processors. Code compiled for the IBM 603/750 (Apple G3) functions without issue on a Freescale 74xx (Apple G4), IBM 970 (Apple G5), IBM pSeries (POWER4, POWER5, POWER6), PA Semi PWRficient, and the new Sony-Toshiba-IBM (STI) Cell Broadband Engine whose PPE (Primary Processing Element; one of 9 on-board cores) is essentially a single core 970, including the AltiVec 128-bit vector processor.

While GCC now includes compile-time flags to support the AltiVec unit, development tools for the Cell processor come in a variety of forms, both freely available and as commercial products with a growing pool of on-line knowledge and support.


  The Cell Broadband Engine
Cell is a microprocessor architecture jointly developed by Sony Computer Entertainment, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001. Cell combines a general-purpose Power Architecture core (PPE/PPU) of modest performance with streamlined coprocessing elements (SPEs/SPUs) which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.

While code build for other Power based architectures will run without recompile on the Cell PPE, to take full advantage of the Cell/B.E. it is important to optimize the code for the SPEs. The following are HOWTOs, tutorials, and examples for programming with and optimizing for the Cell Broadband Engine.


Introduction to Cell
Tutorials and HowTos
Languages & Resources
Sample Code



 
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